12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04) Napa, California April 20-April 23 ISBN: 0-7695-2230-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FCCM.2004.45
We present algorithms to perform power-driven partitioning and formulate two applications within this domain: chip-level power management for multi-FPGA systems and single chip power optimization using localized voltage scaling. We tested the effectiveness of our approach on a set of LUT-level benchmark netlists. Savings in power consumption with our approach are 19.18% (as high as 32.28) and 14.78 % on average (as high as 25.79%) when partitioning is performed under resource constraints. If the number of partitions is not restricted, power improvements as high as 54 % are achievable.
Citation:
Rajarshi Mukherjee, Seda Ogrenci Memik, "Power Management for FPGAs: Power-Driven Design Partitioning," fccm, pp.326-327, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04), 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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