An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed Arithmetic

F
FCCM
2004
12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04)
Abstract - An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed Arithmetic

	This Article
	PDF RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Daniel J. Allred Articles by Walter Huang Articles by Venkatesh Krishnan Articles by Heejong Yoo Articles by David V. Anderson

12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04)

An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed Arithmetic (PDF)

Napa, California

April 20-April 23

ISBN: 0-7695-2230-0

	ASCII Text	x
	Daniel J. Allred, Walter Huang, Venkatesh Krishnan, Heejong Yoo, David V. Anderson, "An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed Arithmetic," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 324-325, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04), 2004.

	BibTex	x
	@article{ 10.1109/FCCM.2004.15, author = {Daniel J. Allred and Walter Huang and Venkatesh Krishnan and Heejong Yoo and David V. Anderson}, title = {An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed Arithmetic}, journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on}, volume = {0}, year = {2004}, isbn = {0-7695-2230-0}, pages = {324-325}, doi = {http://doi.ieeecomputersociety.org/10.1109/FCCM.2004.15}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on TI - An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed Arithmetic SN - 0-7695-2230-0 SP324 EP325 A1 - Daniel J. Allred, A1 - Walter Huang, A1 - Venkatesh Krishnan, A1 - Heejong Yoo, A1 - David V. Anderson, PY - 2004 KW - null VL - 0 JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on ER -

Daniel J. Allred, Georgia Institute of Technology, Atlanta, GA

Walter Huang, Georgia Institute of Technology, Atlanta, GA

Venkatesh Krishnan, Georgia Institute of Technology, Atlanta, GA

Heejong Yoo, Georgia Institute of Technology, Atlanta, GA

David V. Anderson, Georgia Institute of Technology, Atlanta, GA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FCCM.2004.15

In this paper, an FIR adaptive filter implementation using a multiplier-free architecture is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with a series of look-up-table (LUT) accesses. This can be achieved at the cost of a moderate increase in memory usage. The proposed design performs an LMS-type adaptation on a sample-by-sample basis. This is accomplished by an innovative LUT update using a matched auxiliary LUT. The system is implemented on an FPGA that enables rapid prototyping of digital circuits. Implementation results are provided to demonstrate that a high-speed LMS adaptive filter can be realized employing the proposed architecture.

Citation:

Daniel J. Allred, Walter Huang, Venkatesh Krishnan, Heejong Yoo, David V. Anderson, "An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed Arithmetic," fccm, pp.324-325, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04), 2004

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.