Proceedings of The 26th EUROMICRO Conference (EUROMICRO'00)-Volume 2 Parallel Multiplier Designs Utilizing A Non-Binary Logic Scheme Maastricht, The Netherlands September 05-September 07 ISBN: 0-7695-0780-8
This paper presents a novel approach for CMOS low-power, high performance parallel multiplier design, utilizing a recently proposed binary shift switch logic scheme. Compared with the existing well-known parallel multiplier designs, the new approach requires fewer partial product bit reduction stages, and improves performance in speed, VLSI area as well as power dissipation. SPICE simulations with a 0.25-micron, 2.5-volt supply process on critical paths have demonstrated the superiority of the approach.
Index Terms:
Arithmetic circuit, parallel counter and compressor, partial product reduction, low power high performance CMOS circuit design, VLSI design
Citation:
Rong Lin, "Parallel Multiplier Designs Utilizing A Non-Binary Logic Scheme," euromicro, vol. 2, pp.2456, Proceedings of The 26th EUROMICRO Conference (EUROMICRO'00)-Volume 2, 2000 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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