In the paper a new method is proposed for multilevel logic synthesis based on functional decomposition into gates. Unlike the traditional approach to the decomposition, where the basic components of the decomposition network are the universal cells, we propose a method, which instead of cells uses gates, but preserves advantages of the functional decomposition. This approach makes possible to improve traditional FPGA functional decomposition onto the more general algorithm, which is also useful for other technologies in VLSI ASIC design.