One of the main bottlenecks when using massively parallel processors, both RISC and CISC, and VLIW style processors has been the identi.cation of potential parallelism in the tasks. Recently, multi-threaded techniques for exploiting instruction- and data-level parallelism have gained renewed interest since high degrees of pipelining, caused by the increasing clock frequencies, introduce extra dependencies between instructions. Sophisticated methods implementing branch prediction and pipeline flushing during interrupts must be adopted, which in addition puts more requirements onto the compilers.

We present an Interleaved Processing architecture we call the Revolver Architecture together with a technique we call Register File Folding, which relieves the MIMD architecture of these dependencies to allow for Collision Free Computing. We also discuss the implementation of the Revolver as a multi-threaded processor core, based on our presented techniques, together with some architectural strategies for implementing the Revolver Architecture as a DSP core.