23rd EUROMICRO Conference '97 New Frontiers of Information Technology RT level testability analysis to reduce test application time Budapest, HUNGARY September 01-September 04 ISBN: 0-8186-8129-2
Describes research activities, the goal of which is to develop a methodology that solves the problem of RT (register transfer) level (RTL) testability analysis in a complex way. On the basis of the RTL testability analysis, a substantial reduction in test application time can be achieved. A new model of RTL element classification for the purposes of RTL testability analysis is described. The prescription for an RTL circuit transformation to a labelled directed graph and its representation in a PROLOG environment are presented. The methodology for the RTL testability analysis and the principles of its implementation are described.
Index Terms:
logic testing; register transfer level testability analysis; test application time reduction; RTL element classification; RTL circuit transformation; labelled directed graph; PROLOG environment; implementation principles
Citation:
Z. Kotasek, F. Zboril, "RT level testability analysis to reduce test application time," euromicro, pp.104, 23rd EUROMICRO Conference '97 New Frontiers of Information Technology, 1997 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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