The evolution of the technology in search of smaller and faster devices brings along the need for a new paradigm in the design of circuits tolerant to soft errors. The current assumption of transient pulses shorter than the cycle time of the circuit will no longer be true, thereby precluding the use of most of the mitigation techniques proposed so far. With transient faults duration spanning more than one clock cycle of operation, new fault tolerance solutions, working at the system level, with low area and performance overheads, must be devised. In this paper we propose the first steps in the direction of using low cost verification schemes at the algorithmic level, applied to general purpose matrix multiplication applications. Experimental results obtained with two different implementations of checker circuits using the proposed technique are presented and discussed.