SRAM-based Field Programmable Gate Arrays (FPGAs) are very sensitive to Single Event Upsets (SEUs) affecting their configuration memory. SEUs may have critical effects on the circuit FPGA devices implement. In order to deploy safety- or mission-critical applications on SRAM-based FPGAs, designers need to adopt hardening techniques, as well as methodologies for estimating and validating the SEU?s sensitivity of the obtained applications in the early design phase. In this paper we describe a new methodology for predict the effects of SEUs by combining static and dynamic analysis of the circuit?s FPGA implements. The proposed methodology is able to identify the critical single event upset locations within the configuration memory and to provide a detailed classification of the provoked effects. Experimental results on several realistic applications demonstrate the feasibility of the proposed methodology.