PLLs are the heart of most SoCs, so their performance affects many tests. Practical, published PLL BIST approaches cannot measure \le10 ps RMS jitter or \ge1 GHz. This paper describes how a SerDes undersampling DFT technique was adapted to test multiple PLLs and DLLs for jitter, output frequency, duty cycle, and other parameters. Its multi-GHz range, sub-picosecond jitter noise floor, and minimal silicon area are better than for any previous silicon-proven DFT or BIST that needs no calibration or analog circuitry. FPGA implementation results are provided.