In this paper, two wrapper designs are proposed for core-based test application based on Networks-on-Chip (NoC) reuse. It will be shown that the previously proposed NoC wrapper does not efficiently utilize the NoC bandwidth, which may result in poor test schedules. Our wrappers (Type 1 and Type 2) complement each other to overcome this inefficiency while minimizing the overhead. The Type 2 wrapper uses larger area overhead to increase bandwidth efficiency, while the Type 1 takes advantage of some special configurations which may not require a complex and high-cost wrapper. Two wrapper optimization algorithms are applied to both wrapper designs under channel bandwidth and test time constraints, resulting in very little or no increase in the test application time compared to conventional TAM approaches.