12th IEEE European Test Symposium (ETS'07) Embedded Tutorial on Low Power Test Freiburg, Germany May 20-May 24 ISBN: 0-7695-2827-9
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ETS.2007.22
Excessive power during test affects the reliability of digital integrated circuits, test throughput and manufacturing yield. Numerous low power test methods have been investigated over the past decade and new power-aware automatic test pattern generation, design-for-test and test planning techniques have emerged. This embedded tutorial introduces the topic of low power test and it overviews the basic techniques and some recent advancements in this field.
Citation:
Nicola Nicolici, Xiaoqing Wen, "Embedded Tutorial on Low Power Test," ets, pp.202-210, 12th IEEE European Test Symposium (ETS'07), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||