Automatic Generation of Instructions to Robustly Test Delay Defects in Processors

E
ETS
2007
12th IEEE European Test Symposium (ETS'07)
Abstract - Automatic Generation of Instructions to Robustly Test Delay Defects in Processors

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Sankar Gurumurthy Articles by Ramtilak Vemu Articles by Jacob A. Abraham Articles by Daniel G. Saab

12th IEEE European Test Symposium (ETS'07)

Freiburg, Germany

May 20-May 24

ISBN: 0-7695-2827-9

	ASCII Text	x
	Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Daniel G. Saab, "Automatic Generation of Instructions to Robustly Test Delay Defects in Processors," European Test Symposium, IEEE, pp. 173-178, 12th IEEE European Test Symposium (ETS'07), 2007.

	BibTex	x
	@article{ 10.1109/ETS.2007.13, author = {Sankar Gurumurthy and Ramtilak Vemu and Jacob A. Abraham and Daniel G. Saab}, title = {Automatic Generation of Instructions to Robustly Test Delay Defects in Processors}, journal ={European Test Symposium, IEEE}, volume = {0}, year = {2007}, issn = {1530-1877}, pages = {173-178}, doi = {http://doi.ieeecomputersociety.org/10.1109/ETS.2007.13}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - European Test Symposium, IEEE TI - Automatic Generation of Instructions to Robustly Test Delay Defects in Processors SN - 1530-1877 SP173 EP178 A1 - Sankar Gurumurthy, A1 - Ramtilak Vemu, A1 - Jacob A. Abraham, A1 - Daniel G. Saab, PY - 2007 KW - null VL - 0 JA - European Test Symposium, IEEE ER -

Sankar Gurumurthy, The University of Texas at Austin, USA

Ramtilak Vemu, The University of Texas at Austin, USA

Jacob A. Abraham, The University of Texas at Austin, USA

Daniel G. Saab, Case Western Reserve University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ETS.2007.13

We present a technique for generating instruction sequences to test a processor functionally. We target delay defects with this technique using an ATPG engine to generate delay tests locally, a verification engine to map the tests globally, and a feedback mechanism that makes the entire procedure faster. We demonstrate nearly 96% coverage of delay faults with the instruction sequences generated. These instruction sequences can be loaded into the cache to test the processor functionally.

Citation:

Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Daniel G. Saab, "Automatic Generation of Instructions to Robustly Test Delay Defects in Processors," ets, pp.173-178, 12th IEEE European Test Symposium (ETS'07), 2007

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.