Eleventh IEEE European Test Symposium (ETS'06) On-Chip Test Generation Using Linear Subspaces Southampton, United Kingdom May 21-May 21 ISBN: 0-7695-2566-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ETS.2006.35
A central problem in built-in self test (BIST) is how to efficiently generate a small set of test vectors that detect all targeted faults. We propose a novel solution that uses linear algebraic concepts to partition the vector space of tests into subspaces (clusters). A subspace is defined by a compact set of basis vectors. We give an algorithm to compute sets of basis vectors defining the clusters. We also describe a low-cost logic circuit based on Gray codes that reproduces the subspaces from these basis vectors. Experimental results are presented which show that this approach reduces on-chip hardware overhead and test application time, while also guaranteeing full fault coverage.
Citation:
Ramashis Das, Igor L. Markov, John P. Hayes, "On-Chip Test Generation Using Linear Subspaces," ets, pp.111-116, Eleventh IEEE European Test Symposium (ETS'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||