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Eleventh IEEE European Test Symposium (ETS'06)
Fault Injection-based Reliability Evaluation of SoPCs
Southampton, United Kingdom
May 21-May 21
ISBN: 0-7695-2566-0
M. Sonza Reorda, Politecnico di Torino, Italy
L. Sterpone, Politecnico di Torino, Italy
M. Violante, Politecnico di Torino, Italy
M. Portela-Garcia, Universidad Carlos III de Madrid, Spain
C. Lopez-Ongil, Universidad Carlos III de Madrid, Spain
L. Entrena, Universidad Carlos III de Madrid, Spain
Systems-on-Programmable-Chip (SoPCs) include processors, memories and programmable logic that allow to catch multiple application requirements such as high performance, reconfigurability and low-costs. Due to these characteristics, they are also becoming very attractive for safety-critical applications. However, the issue of assessing the reliability they can provide and debugging the possible safety-related mechanisms they embed is still open. In this paper, we present a new fault-injection approach for evaluating the impact of transient faults in SoPCs. Fault-injection experiments are reported on a case study consisting of a web server implemented on a Xilinx Virtex-II FPGA embedding a PowerPC 405 and running the whole TCP/IP stack.
Citation:
M. Sonza Reorda, L. Sterpone, M. Violante, M. Portela-Garcia, C. Lopez-Ongil, L. Entrena, "Fault Injection-based Reliability Evaluation of SoPCs," ets, pp.75-82, Eleventh IEEE European Test Symposium (ETS'06), 2006
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