Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator

P
PDP
2002
10th Euromicro Workshop on Parallel, Distributed and Network-based Processing (EUROMICRO-PDP 2002)
Abstract - Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator

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10th Euromicro Workshop on Parallel, Distributed and Network-based Processing (EUROMICRO-PDP 2002)

Canary Islands, Spain

January 09-January 11

ISBN: 0-7695-1444-8

	ASCII Text	x
	Mario Porrmann, Ulf Witkowski, Heiko Kalte, Ulrich Rückert, "Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator," Parallel, Distributed, and Network-Based Processing, Euromicro Conference on, pp. 0243, 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing (EUROMICRO-PDP 2002), 2002.

	BibTex	x
	@article{ 10.1109/EMPDP.2002.994279, author = {Mario Porrmann and Ulf Witkowski and Heiko Kalte and Ulrich Rückert}, title = {Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator}, journal ={Parallel, Distributed, and Network-Based Processing, Euromicro Conference on}, volume = {0}, year = {2002}, issn = {1066-6192}, pages = {0243}, doi = {http://doi.ieeecomputersociety.org/10.1109/EMPDP.2002.994279}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Parallel, Distributed, and Network-Based Processing, Euromicro Conference on TI - Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator SN - 1066-6192 SP EP A1 - Mario Porrmann, A1 - Ulf Witkowski, A1 - Heiko Kalte, A1 - Ulrich Rückert, PY - 2002 KW - Artificial Neural Networks KW - Reconfigurable KW - Hardware Accelerator KW - FPGA KW - RBF KW - Kohonen KW - Self-organizing Map KW - Associative Memory VL - 0 JA - Parallel, Distributed, and Network-Based Processing, Euromicro Conference on ER -

Mario Porrmann, University of Paderborn

Ulf Witkowski, University of Paderborn

Heiko Kalte, University of Paderborn

Ulrich Rückert, University of Paderborn

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/EMPDP.2002.994279

The hardware implementation of three different artificial neural networks is presented. The basis for the implementation is the reconfigurable hardware accelerator RAPTOR2000, which is based on FPGAs. The investigated neural network architectures are neural associative memories, self-organizing feature maps and basis function networks. Some of the key implementational issues are considered. Especially resource-efficiency and performance of the presented realizations are discussed.

Index Terms:

Artificial Neural Networks, Reconfigurable, Hardware Accelerator, FPGA, RBF, Kohonen, Self-organizing Map, Associative Memory

Citation:

Mario Porrmann, Ulf Witkowski, Heiko Kalte, Ulrich Rückert, "Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator," pdp, pp.0243, 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing (EUROMICRO-PDP 2002), 2002

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