4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96)
Performance of Shared Cache on Multithreaded Architectures
PORTUGAL
January 24-January 26
ISBN: 0-8186-7376-1
Yunn-Yen Chen, Comput. & Commun. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Jih-Kwon Peir, Comput. & Commun. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Chung-Ta King, Comput. & Commun. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Abstract: Uses a trace-driven simulation technique to study the performance impact on the storage hierarchy system in a multithreaded execution environment. Particularly, we examine the effects of different multithread scheduling techniques on cache performance using several program traces representing a typical server/workstation workload mix. An MRU (most recently used) priority scheduling scheme is proposed as the baseline scheduling scheme to study the performance effects. We found that the cache performance can be improved over the traditional round-robin scheduling method when the thread with the MRU hit is given a higher priority. With a direct-map cache, the absolute hit ratio can be improved by 7% more than the original ratio. We also studied the performance effects on cache memory with a varying number of concurrent threads. The results showed that both the cache size and the set associativity need to increase according to the number of threads, in order to maintain a comparable cache performance. The main contribution of this paper is to provide a performance comparison between two simple schemes which are easy to implement with the proposed baseline scheme.
Index Terms:
cache storage; parallel architectures; performance evaluation; shared memory systems; processor scheduling; simulation; shared cache performance; multithreaded architectures; trace-driven simulation technique; storage hierarchy system; multithreaded execution environment; multithread scheduling techniques; program traces; server/workstation workload mix; MRU priority scheduling scheme; round-robin scheduling method; direct-map cache; absolute hit ratio; concurrent threads; cache size; set associativity
Citation:
Yunn-Yen Chen, Jih-Kwon Peir, Chung-Ta King, "Performance of Shared Cache on Multithreaded Architectures," pdp, pp.0541, 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), 1996