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4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96)
Parallel Graph Reduction with the PACE Architecture
PORTUGAL
January 24-January 26
ISBN: 0-8186-7376-1
ASCII Text
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M.E. Waite, T.J. Reynolds, F.Z. Ieromnimon, "Parallel Graph Reduction with the PACE Architecture," Parallel, Distributed, and Network-Based Processing, Euromicro Conference on, pp. 0448, 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), 1996.
 
 
BibTex
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@article{ 10.1109/EMPDP.1996.500618,
author = {M.E. Waite and T.J. Reynolds and F.Z. Ieromnimon},
title = {Parallel Graph Reduction with the PACE Architecture},
journal ={Parallel, Distributed, and Network-Based Processing, Euromicro Conference on},
volume = {0},
year = {1996},
isbn = {0-8186-7376-1},
pages = {0448},
doi = {http://doi.ieeecomputersociety.org/10.1109/EMPDP.1996.500618},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel, Distributed, and Network-Based Processing, Euromicro Conference on
TI - Parallel Graph Reduction with the PACE Architecture
SN - 0-8186-7376-1
SP
EP
A1 - M.E. Waite,
A1 - T.J. Reynolds,
A1 - F.Z. Ieromnimon,
PY - 1996
KW - distributed memory systems; parallel architectures; parallel programming; graph theory; virtual machines; parallel graph reduction; PACE architecture; distributed memory multiprocessor; graph reduction model; basic replicable node; prototype version; parallel execution; Verilog description; C simulator
VL - 0
JA - Parallel, Distributed, and Network-Based Processing, Euromicro Conference on
ER -
 
M.E. Waite, Dept. of Comput. Sci., Essex Univ., Colchester, UK
T.J. Reynolds, Dept. of Comput. Sci., Essex Univ., Colchester, UK
F.Z. Ieromnimon, Dept. of Comput. Sci., Essex Univ., Colchester, UK
Abstract: The PACE architecture is an extensible, distributed memory multiprocessor that is designed specifically to support the graph reduction model of computation. PACE differs from most other research projects in this area in that it advocates the use of a specially designed processor, rather than currently available devices, as the basic replicable node. We present the design of a prototype version of the new processor, together with the latest results obtained by simulating the parallel execution of example programs on both a detailed Verilog description of the hardware and a much faster C simulator (arrays of up to 200 processors are simulated).
Index Terms:
distributed memory systems; parallel architectures; parallel programming; graph theory; virtual machines; parallel graph reduction; PACE architecture; distributed memory multiprocessor; graph reduction model; basic replicable node; prototype version; parallel execution; Verilog description; C simulator
Citation:
M.E. Waite, T.J. Reynolds, F.Z. Ieromnimon, "Parallel Graph Reduction with the PACE Architecture," pdp, pp.0448, 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), 1996
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