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4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96)
Design and Implementation of the Control Structure of the PAPRICA-3 Processor
PORTUGAL
January 24-January 26
ISBN: 0-8186-7376-1
ASCII Text
x 
 
F. Gregoretti, F. Intini, L. Lavagno, R. Passerone, L.M. Reyneri, "Design and Implementation of the Control Structure of the PAPRICA-3 Processor," Parallel, Distributed, and Network-Based Processing, Euromicro Conference on, pp. 0290, 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), 1996.
 
 
BibTex
x
 
@article{ 10.1109/EMPDP.1996.500599,
author = {F. Gregoretti and F. Intini and L. Lavagno and R. Passerone and L.M. Reyneri},
title = {Design and Implementation of the Control Structure of the PAPRICA-3 Processor},
journal ={Parallel, Distributed, and Network-Based Processing, Euromicro Conference on},
volume = {0},
year = {1996},
isbn = {0-8186-7376-1},
pages = {0290},
doi = {http://doi.ieeecomputersociety.org/10.1109/EMPDP.1996.500599},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel, Distributed, and Network-Based Processing, Euromicro Conference on
TI - Design and Implementation of the Control Structure of the PAPRICA-3 Processor
SN - 0-8186-7376-1
SP
EP
A1 - F. Gregoretti,
A1 - F. Intini,
A1 - L. Lavagno,
A1 - R. Passerone,
A1 - L.M. Reyneri,
PY - 1996
KW - pipeline processing; parallel architectures; image processing equipment; image processing; real-time systems; control structure; PAPRICA-3 processor; pipeline architecture; instruction execution; linear array processor PAPRICA-9; array processor; algorithmic efficiency; image recognition; embedded systems; real time image processing; multi path queue structure; application programs
VL - 0
JA - Parallel, Distributed, and Network-Based Processing, Euromicro Conference on
ER -
 
F. Gregoretti, Dipartimento di Elettronica, Politecnico di Torino, Italy
F. Intini, Dipartimento di Elettronica, Politecnico di Torino, Italy
L. Lavagno, Dipartimento di Elettronica, Politecnico di Torino, Italy
R. Passerone, Dipartimento di Elettronica, Politecnico di Torino, Italy
L.M. Reyneri, Dipartimento di Elettronica, Politecnico di Torino, Italy
Abstract: The paper describes the pipeline architecture designed to control the execution of instructions on the linear array processor PAPRICA-9, which is being developed at the Politecnico di Torino. The main applications of the array processor lay in the area of image processing, image recognition, embedded systems for guidance assistance and the like. Exploitation of this architecture is currently investigated in the area of real time image processing, a very demanding task in terms of overall performance. Our design is aimed at improving the algorithmic efficiency by taking advantage of a multi path queue structure which allows different instructions to run simultaneously, and by optimizing particular patterns of instructions which often appear in envisaged application programs.
Index Terms:
pipeline processing; parallel architectures; image processing equipment; image processing; real-time systems; control structure; PAPRICA-3 processor; pipeline architecture; instruction execution; linear array processor PAPRICA-9; array processor; algorithmic efficiency; image recognition; embedded systems; real time image processing; multi path queue structure; application programs
Citation:
F. Gregoretti, F. Intini, L. Lavagno, R. Passerone, L.M. Reyneri, "Design and Implementation of the Control Structure of the PAPRICA-3 Processor," pdp, pp.0290, 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), 1996
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