Simulating Asynchronous Architectures on Transputer Networks

P
PDP
1996
4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96)
Abstract - Simulating Asynchronous Architectures on Transputer Networks

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	Similar Articles Articles by G. Theodoropoulos Articles by J.V. Woods

4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96)

PORTUGAL

January 24-January 26

ISBN: 0-8186-7376-1

	ASCII Text	x
	G. Theodoropoulos, J.V. Woods, "Simulating Asynchronous Architectures on Transputer Networks," Parallel, Distributed, and Network-Based Processing, Euromicro Conference on, pp. 0274, 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), 1996.

	BibTex	x
	@article{ 10.1109/EMPDP.1996.500597, author = {G. Theodoropoulos and J.V. Woods}, title = {Simulating Asynchronous Architectures on Transputer Networks}, journal ={Parallel, Distributed, and Network-Based Processing, Euromicro Conference on}, volume = {0}, year = {1996}, isbn = {0-8186-7376-1}, pages = {0274}, doi = {http://doi.ieeecomputersociety.org/10.1109/EMPDP.1996.500597}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Parallel, Distributed, and Network-Based Processing, Euromicro Conference on TI - Simulating Asynchronous Architectures on Transputer Networks SN - 0-8186-7376-1 SP EP A1 - G. Theodoropoulos, A1 - J.V. Woods, PY - 1996 KW - transputer systems; parallel architectures; parallel languages; circuit analysis computing; Occam; asynchronous circuits; logic design; asynchronous architecture simulation; transputer networks; asynchronous design techniques; asynchronous logic; clock related timing problems; Occam; CSP based parallel language; asynchronous architectural simulation models VL - 0 JA - Parallel, Distributed, and Network-Based Processing, Euromicro Conference on ER -

G. Theodoropoulos, Dept. of Comput. Sci., Manchester Univ., UK

J.V. Woods, Dept. of Comput. Sci., Manchester Univ., UK

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/EMPDP.1996.500597

Abstract: Recently, there has been a resurgence of interest in asynchronous design techniques due to the potential of asynchronous logic for higher performance, power efficiency and immunity from clock related timing problems. Occam, a CSP based parallel language provides for the rapid development of asynchronous architectural simulation models which may then be executed on a transputer network to achieve high performance. The paper discusses issues related to the design and execution of such models.

Index Terms:

transputer systems; parallel architectures; parallel languages; circuit analysis computing; Occam; asynchronous circuits; logic design; asynchronous architecture simulation; transputer networks; asynchronous design techniques; asynchronous logic; clock related timing problems; Occam; CSP based parallel language; asynchronous architectural simulation models

Citation:

G. Theodoropoulos, J.V. Woods, "Simulating Asynchronous Architectures on Transputer Networks," pdp, pp.0274, 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), 1996

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