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3rd Euromicro Workshop on Parallel and Distributed Processing
A distributed computer architecture for qualitative simulation based on a multi-DSP and FPGAs
San Remo, Italy
January 25-January 27
ISBN: 0-8186-7031-2
ASCII Text
x 
 
M. Platzner, B. Rinner, R. Weiss, "A distributed computer architecture for qualitative simulation based on a multi-DSP and FPGAs," Parallel, Distributed, and Network-Based Processing, Euromicro Conference on, pp. 311, 3rd Euromicro Workshop on Parallel and Distributed Processing, 1995.
 
 
BibTex
x
 
@article{ 10.1109/EMPDP.1995.389193,
author = {M. Platzner and B. Rinner and R. Weiss},
title = {A distributed computer architecture for qualitative simulation based on a multi-DSP and FPGAs},
journal ={Parallel, Distributed, and Network-Based Processing, Euromicro Conference on},
volume = {0},
year = {1995},
issn = {1066-6192},
pages = {311},
doi = {http://doi.ieeecomputersociety.org/10.1109/EMPDP.1995.389193},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel, Distributed, and Network-Based Processing, Euromicro Conference on
TI - A distributed computer architecture for qualitative simulation based on a multi-DSP and FPGAs
SN - 1066-6192
SP
EP
A1 - M. Platzner,
A1 - B. Rinner,
A1 - R. Weiss,
PY - 1995
KW - parallel architectures; special purpose computers; digital simulation; distributed computer architecture; qualitative simulation; multi-DSP; FPGAs; computer architecture; hardware design; application-specific computer architecture; design strategies; performance; constraint-check-function
VL - 0
JA - Parallel, Distributed, and Network-Based Processing, Euromicro Conference on
ER -
 
M. Platzner, Inst. for Tech. Inf., Graz Univ. of Technol., Austria
B. Rinner, Inst. for Tech. Inf., Graz Univ. of Technol., Austria
R. Weiss, Inst. for Tech. Inf., Graz Univ. of Technol., Austria
The design of a specialized computer architecture for qualitative simulation is presented. Our interest focuses on the hardware design of an application-specific computer architecture which is composed of programmable processors (digital signal processors TMS320C40) and application-specific integrated circuits (FPGAs). Two design strategies are considered to improve the performance. Primitive functions are hardware-implemented using FPGAs (software/hardware migration). More complex functions are mapped onto a multi processor system formed by TMS320C40. This computer architecture is designed for the well known algorithm for qualitative simulation-QSIM. In this paper we present the design of a computer architecture for the constraint-check-function-a function of the QSIM kernel.
Index Terms:
parallel architectures; special purpose computers; digital simulation; distributed computer architecture; qualitative simulation; multi-DSP; FPGAs; computer architecture; hardware design; application-specific computer architecture; design strategies; performance; constraint-check-function
Citation:
M. Platzner, B. Rinner, R. Weiss, "A distributed computer architecture for qualitative simulation based on a multi-DSP and FPGAs," pdp, pp.311, 3rd Euromicro Workshop on Parallel and Distributed Processing, 1995
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