Using a massively parallel architecture for integrated circuits testing

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	Similar Articles Articles by F. Gregoretti Articles by C. Passerone

3rd Euromicro Workshop on Parallel and Distributed Processing

San Remo, Italy

January 25-January 27

ISBN: 0-8186-7031-2

	ASCII Text	x
	F. Gregoretti, C. Passerone, "Using a massively parallel architecture for integrated circuits testing," Parallel, Distributed, and Network-Based Processing, Euromicro Conference on, pp. 332, 3rd Euromicro Workshop on Parallel and Distributed Processing, 1995.

	BibTex	x
	@article{ 10.1109/EMPDP.1995.389190, author = {F. Gregoretti and C. Passerone}, title = {Using a massively parallel architecture for integrated circuits testing}, journal ={Parallel, Distributed, and Network-Based Processing, Euromicro Conference on}, volume = {0}, year = {1995}, issn = {1066-6192}, pages = {332}, doi = {http://doi.ieeecomputersociety.org/10.1109/EMPDP.1995.389190}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Parallel, Distributed, and Network-Based Processing, Euromicro Conference on TI - Using a massively parallel architecture for integrated circuits testing SN - 1066-6192 SP EP A1 - F. Gregoretti, A1 - C. Passerone, PY - 1995 KW - parallel architectures; integrated circuit testing; image processing; massively parallel architecture; integrated circuits testing; Scanning Electron Microscopy; Integrated Circuits; VLSI integrated circuit; prototype; low level image processing VL - 0 JA - Parallel, Distributed, and Network-Based Processing, Euromicro Conference on ER -

F. Gregoretti, Dipartimento di Elettronica, Politecnico di Torino, Italy

C. Passerone, Dipartimento di Elettronica, Politecnico di Torino, Italy

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/EMPDP.1995.389190

The paper describes the application of a prototype of a massively parallel processing machine to the acceleration of a number of tasks in the debugging of Integrated Circuits by the use of Scanning Electron Microscopy. In particular the machine is used in a number of low level image processing tasks taking advantage in some cases of the specific characteristics of the images of the surface of a VLSI integrated circuit. Preliminary results show that, even with the current experimental prototype, the performance figures for these tasks are one order of magnitude better than those of a state of the art workstation.

Index Terms:

parallel architectures; integrated circuit testing; image processing; massively parallel architecture; integrated circuits testing; Scanning Electron Microscopy; Integrated Circuits; VLSI integrated circuit; prototype; low level image processing

Citation:

F. Gregoretti, C. Passerone, "Using a massively parallel architecture for integrated circuits testing," pdp, pp.332, 3rd Euromicro Workshop on Parallel and Distributed Processing, 1995

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