This paper presents a power-optimized evolvable hardware (EHW) architecture that employs custom reconfigurable technology. It comprises a preliminary research work towards the implementation of filtering circuits associated with the JPL-Boeing micro-machined gyroscope. Our scope is to implement a low-power, autonomously reconfigurable architecture that is tailored for the realization of arbitrary response FIR filters. For the purpose of this paper the hardware substrate comprises a reconfigurable 4x12 array, which consists of heterogeneous, configurable, arithmetic-logic units (CALUs). The implementation of the design is based on the primitive operator filter (POF) technique in order to evolve all the parts of a filter (unconstrained filter). Furthermore, a hybrid arithmetic approach is employed in order for the architecture to cope with overflow events. The paradigms of both lowpass and highpass filters are produced, using two different strategies of evolution. The obtained results demonstrate the physical characteristics of the reconfigurable substrate and the performance of the genetic algorithm (GA) in successfully designing FIR filters. Finally, the power results of the reconfigurable architecture (RA) are compared with these of the AT6000 series FPGAs and an algorithmically power-optimized, custom reprogrammable FIR core.