The problem of scale has left the Evolvable Hardware (EHW) community wondering about the viability of this approach as an alternative design methodology for large and practical circuits. Despite the move from conventional direct mapped techniques to developmental approaches, so far only small circuits have been evolved. This paper shows that, by partitioning a digital circuit and making use of a developmental approach, namely the Developmental Cartesian Genetic Programming (DCGP) technique, it is possible to evolve large circuits. The advantages of this approach with respect to evolution time, area overhead and fault tolerance are highlighted for different adder and multiplier circuits and the ISCAS'89-benchmark circuit rd84. This concept can be easily extended to any combinational circuit, thus proving that this is a viable solution towards evolving large and complex circuits.