This paper introduces an approach showing that a complete implementation of a digital evolvable hardware system can automatically be created from a high-level specification. The approach generates the implementation of a virtual reconfigurable circuit and evolutionary algorithm independently of a target platform, i.e. as a soft IP core. The method is evaluated on the development of two high-performance evolvable systems that are utilized for fast evolutionary design of small combinational circuits, such as 3 ? 3-bit multipliers. The COMBO6 card is employed for these experiments.