This paper describes the application of intrinsic evolvable hardware to combinational circuit design and synthesis, as an alternative to conventional approaches. This novel reconfigurable architecture is inspired by Cartesian Genetic Programming and dedicated for implementing high performance digital image filters on a custom Xilinx Virtex FPGA xcv1000, together with a flexible local interconnection hierarchy. As a highly parallel architecture, it scales linearly with the filter complexity. It is reconfigured by an external genetic reconfiguration processing unit with a hardware GA implementation embedded. Due to pipelining, parallelization and no function call overhead, it yields a significant speedup of one to two orders of magnitude over a software implementation, which is especially useful for the real-time applications. The experimental results conclude that in terms of computational effort, filtered image signal and implementation cost, the intrinsic evolvable hardware solution outperforms traditional approaches.