Power Dissipation Reductions with Genetic Algorithms

E
EH
2003
2003 NASA/DoD Conference on Evolvable Hardware (EH'03)
Abstract - Power Dissipation Reductions with Genetic Algorithms

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Eiichi Takahashi Articles by Masahiro Murakawa Articles by Yuji Kasai Articles by Tetsuya Higuchi

2003 NASA/DoD Conference on Evolvable Hardware (EH'03)

Chicago, Illinois

July 09-July 11

ISBN: 0-7695-1977-6

	ASCII Text	x
	Eiichi Takahashi, Masahiro Murakawa, Yuji Kasai, Tetsuya Higuchi, "Power Dissipation Reductions with Genetic Algorithms," Evolvable Hardware, NASA/DoD Conference on, pp. 111, 2003 NASA/DoD Conference on Evolvable Hardware (EH'03), 2003.

	BibTex	x
	@article{ 10.1109/EH.2003.1217654, author = {Eiichi Takahashi and Masahiro Murakawa and Yuji Kasai and Tetsuya Higuchi}, title = {Power Dissipation Reductions with Genetic Algorithms}, journal ={Evolvable Hardware, NASA/DoD Conference on}, volume = {0}, year = {2003}, isbn = {0-7695-1977-6}, pages = {111}, doi = {http://doi.ieeecomputersociety.org/10.1109/EH.2003.1217654}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Evolvable Hardware, NASA/DoD Conference on TI - Power Dissipation Reductions with Genetic Algorithms SN - 0-7695-1977-6 SP EP A1 - Eiichi Takahashi, A1 - Masahiro Murakawa, A1 - Yuji Kasai, A1 - Tetsuya Higuchi, PY - 2003 KW - null VL - 0 JA - Evolvable Hardware, NASA/DoD Conference on ER -

Eiichi Takahashi, MIRAI Project, Adavanced Semiconductor Research Center, AIST

Masahiro Murakawa, MIRAI Project, Adavanced Semiconductor Research Center, AIST

Yuji Kasai, MIRAI Project, Adavanced Semiconductor Research Center, AIST

Tetsuya Higuchi, MIRAI Project, Adavanced Semiconductor Research Center, AIST

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/EH.2003.1217654

Two cases of power dissipation reduction with Pos-tfabrication adjustment using genetic algorithms Are introduced in this paper. The first is a 1GHz ALU implementation, where power consumption has been reduced by 54% through clock-timing adjustment. The second case is the IF (Intermediate Frequency) filter analog LSI used in cellular phones, where the reduction in power dissipation is realized by circuit parameter adjustment. The IF filter has been widely used in commercial cellular phones since 2001.

Citation:

Eiichi Takahashi, Masahiro Murakawa, Yuji Kasai, Tetsuya Higuchi, "Power Dissipation Reductions with Genetic Algorithms," eh, pp.111, 2003 NASA/DoD Conference on Evolvable Hardware (EH'03), 2003

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.