Comparing Different Serial and Parallel Heuristics to Design Combinational Logic Circuits

E
EH
2003
2003 NASA/DoD Conference on Evolvable Hardware (EH'03)
Abstract - Comparing Different Serial and Parallel Heuristics to Design Combinational Logic Circuits

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	Similar Articles Articles by Carlos A. Coello Coello Articles by Enrique Alba Articles by Gabriel Luque Articles by Arturo Hernandez Aguirre

2003 NASA/DoD Conference on Evolvable Hardware (EH'03)

Chicago, Illinois

July 09-July 11

ISBN: 0-7695-1977-6

	ASCII Text	x
	Carlos A. Coello Coello, Enrique Alba, Gabriel Luque, Arturo Hernandez Aguirre, "Comparing Different Serial and Parallel Heuristics to Design Combinational Logic Circuits," Evolvable Hardware, NASA/DoD Conference on, pp. 3, 2003 NASA/DoD Conference on Evolvable Hardware (EH'03), 2003.

	BibTex	x
	@article{ 10.1109/EH.2003.1217635, author = {Carlos A. Coello Coello and Enrique Alba and Gabriel Luque and Arturo Hernandez Aguirre}, title = {Comparing Different Serial and Parallel Heuristics to Design Combinational Logic Circuits}, journal ={Evolvable Hardware, NASA/DoD Conference on}, volume = {0}, year = {2003}, isbn = {0-7695-1977-6}, pages = {3}, doi = {http://doi.ieeecomputersociety.org/10.1109/EH.2003.1217635}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Evolvable Hardware, NASA/DoD Conference on TI - Comparing Different Serial and Parallel Heuristics to Design Combinational Logic Circuits SN - 0-7695-1977-6 SP EP A1 - Carlos A. Coello Coello, A1 - Enrique Alba, A1 - Gabriel Luque, A1 - Arturo Hernandez Aguirre, PY - 2003 KW - null VL - 0 JA - Evolvable Hardware, NASA/DoD Conference on ER -

Carlos A. Coello Coello, Evolutionary Computation Group

Enrique Alba, E.T.S. Ingeniierfa Informatica

Gabriel Luque, E.T.S. Ingeniierfa Informatica

Arturo Hernandez Aguirre, Department of Computer Science

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/EH.2003.1217635

In this paper, we perform a comparative study of different heuristics used to design combinational logic circuits. The use of local search hybridized with a genetic algorithm and the effect of parallelism are of particular interest in the study conducted. Our results indicate that a hybridization of a genetic algorithm with simulated annealing is benefitial and that the use of parallelism does not only introduce a speedup (as expected) in the algorithms, but also allows to improve the quality of the solutions found.

Citation:

Carlos A. Coello Coello, Enrique Alba, Gabriel Luque, Arturo Hernandez Aguirre, "Comparing Different Serial and Parallel Heuristics to Design Combinational Logic Circuits," eh, pp.3, 2003 NASA/DoD Conference on Evolvable Hardware (EH'03), 2003

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