This paper presents a new strategy for design space exploration (DSE) of system-on-chip (SOC) platforms. The solution adopted uses a multi-objective optimization technique based on the concept of Pareto-optimality. The approach is purely heuristic and is a variation of the "simulated annealing" algorithm. To illustrate and validate our methodology the algorithm was used to design a highly parameterized SOC architecture based on a MIPS processor. The performance metrics used to assess the quality of the numerous design alternatives explored are power consumption and execution time. The results obtained demonstrate the robustness of the proposed method both in terms of design time and accuracy.