12th IEEE International Conference and Workshops on the Engineering of Computer-Based Systems (ECBS'05) Reducing the Power Consumption of FPGAs through Retiming Greenbelt, Maryland April 04-April 07 ISBN: 0-7695-2308-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ECBS.2005.58
High power dissipation is one of the major disadvantages of FPGAs. A main part of the power consumed is caused by glitches. This paper analyzes the effect of retiming to reduce the power dissipation of a Xilinx Virtex-II FPGA. The authors introduce a method to insert staging registers into large designs, that are constructed from a high abstraction level language algorithmic description. Results obtained by measurements suggest a high potential for power savings through retiming.
Citation:
Robert Fischer, Klaus Buchenrieder, Ulrich Nageldinger, "Reducing the Power Consumption of FPGAs through Retiming," ecbs, pp.89-94, 12th IEEE International Conference and Workshops on the Engineering of Computer-Based Systems (ECBS'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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