37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07) Processor-Level Selective Replication Edinburgh, UK June 25-June 28 ISBN: 0-7695-2855-4
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSN.2007.75
We propose a processor-level technique called Selective Replication, by which the application can choose where in its application stream and to what degree it requires replication. Recent work on static analysis and fault-injection-based experiments on applications reveals that certain variables in the application are critical to its crash- and hang-free execution. If it can be ensured that only the computation of these variables is error-free, then a high degree of crash/hang coverage can be achieved at a low performance overhead to the application. The Selective Replication technique provides an ideal platform for validating this claim. The technique is compared against complete duplication as provided in current architecture-level techniques. The results show that with about 59% less overhead than full duplication, selective replication detects 97% of the data errors and 87% of the instruction errors that were covered by full duplication. It also reduces the detection of errors benign to the final outcome of the application by 17.8% as compared to full duplication.
Index Terms:
Application-aware, Error Detection, Redundant Hardware, Critical Variable, Duplication.
Citation:
Nithin Nakka, Karthik Pattabiraman, Ravishankar Iyer, "Processor-Level Selective Replication," dsn, pp.544-553, 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||