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International Conference on Dependable Systems and Networks (DSN'06)
Memory-Conscious Reliable Execution on Embedded Chip Multiprocessors
Philadelphia, Pennsylvania
June 25-June 28
ISBN: 0-7695-2607-1
G. Chen, Pennsylvania State University
M. Kandemir, Pennsylvania State University
I. Kolcu, University of Manchester, UK
Code and data duplication has been identified as one of the important mechanisms for improving reliability. In a chip multiprocessor-based execution environment, while it is possible to hide the overhead of code duplication through parallelism, hiding the memory space overhead incurred by data duplication is more difficult. This paper presents a compiler-directed memory-conscious data duplication scheme that tries to minimize the extra memory space required by duplicate execution. The proposed approach achieves this goal by using the memory locations that hold dead data to store the duplicates of the actively-used data. In this way, instead of using extra memory storage for duplicate elements, we use the existing memory locations to the extent allowed by usage patterns of data. The results collected from our experiments clearly show that the proposed approach saves significant memory space, as compared to a straightforward approach that implements full duplication.
Citation:
G. Chen, M. Kandemir, I. Kolcu, "Memory-Conscious Reliable Execution on Embedded Chip Multiprocessors," dsn, pp.13-22, International Conference on Dependable Systems and Networks (DSN'06), 2006
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