2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools VLSI Implementation of a Cryptography-Oriented Reconfigurable Array September 03-September 05 ISBN: 978-0-7695-3277-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2008.127
The long-word and very long-word addition required incryptography applications generally requires custom hardware support provided by ASICs or application-specific instructions in ASIPs. As an alternative to these expensive solutions, FPGAs have been used. To reduce the overhead of commercial FPGAs in implementing cryptography, CryptoRA, a cryptographically-oriented reconfigurable array, has recently been proposed. This paper presents a circuit level implementation of the CryptoRA array which provides the following results: (i) a speed-up of 1.15? to 2.1? from the LUT output to a fast-addition carry path, (ii) a speed-up greater than 1.2? for long-word addition and subtraction, and (iii) these results come at a cost of only an additional 2.5% of a computing tile's silicon area.
Index Terms:
Field-programmable gate arrays, Cryptography, High-speed arithmetic
Citation:
Scott Miller, Ambrose Chu, Mihai Sima, Michael McGuire, "VLSI Implementation of a Cryptography-Oriented Reconfigurable Array," dsd, pp.575-583, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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