10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition Lubeck, Germany August 29-August 31 ISBN: 0-7695-2978-X
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2007.54
This paper proposes a novel approach for increasing the performance of the floating point addition, by efficiently exploiting both paths from the classical double path adder. Thus, it becomes possible to execute two floating point additions simultaneously using a single adder, each on a different path. Performing two floating point additions in this manner will requires duplication of the signs and exponent computation modules. The cost estimates show a 20% increase of the active area for the proposed adder compared with other floating point adders. In terms of performance, the latency of the proposed adder is slightly higher with respect to other double path adders. However, the increased latency is compensated by the increased throughput obtained.
Citation:
Alexandru Amaricai, Mircea Vladuþiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo, "Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition," dsd, pp.132-137, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||