9th EUROMICRO Conference on Digital System Design (DSD'06) Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW Cavtat near Dubrovnik, Croatia August 30-September 01 ISBN: 0-7695-2609-8
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2006.92
The backtrace algorithm lies at the core of many applications, including automatic test pattern generation (ATPG). This paper describes and evaluates an approach for accelerating the backtrace algorithm using conflict-based on-line learning. This approach gets high performance due to large amounts of fine-grain parallelism in the implication process. Architecture of circuits performing backward determination of all input vectors to a given output one is presented as well. The results of this new method are compared with HW implementation of the basic backtrace algorithm proposed recently. The experimental results have been obtained for the ISCAS?85 benchmarks - for those largest, the average growth of an area overhead is about 49 % and the average speed up is about 25 %.
Index Terms:
Backtrace, ATPG, VLSI, on-line learning, hardware, FPGA.
Citation:
Martin St?va, Ondrej Nov?, "Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW," dsd, pp.251-256, 9th EUROMICRO Conference on Digital System Design (DSD'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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