9th EUROMICRO Conference on Digital System Design (DSD'06) Two Architectures of a General Digit-Serial Normal Basis Multiplier Cavtat near Dubrovnik, Croatia August 30-September 01 ISBN: 0-7695-2609-8
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2006.91
We present two architectures of digit-serial normal basis multiplier over GF(2^m). Proposed multipliers are scalable by the digit width of general value in difference of the multiplier of Agnew et al. that may be scaled only by digit width that divides the degree m. This helps designers to trade area for speed e.g. in cryptographic systems, where m should be a prime number. Functionality of multipliers has been tested by simulation and implemented in Xilinx Virtex 4 FPGA.
Citation:
Martin Novotn?, Jan Schmidt, "Two Architectures of a General Digit-Serial Normal Basis Multiplier," dsd, pp.550-553, 9th EUROMICRO Conference on Digital System Design (DSD'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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