The design complexity of systems on a chip drives the need to reuse legacy or intellectual property cores, whose gate-level implementation details are unavailable. The core test depends on manufacturing technologies and changes permanently during a design lifecycle. The purpose of this paper is to assist the designer in the decision making how to test transition faults of re-synthesized intellectual property cores. We have performed various comprehensive experiments with combinational benchmark circuits. The comparison of the detection of the transition faults for different implementations of the circuit was carried out. Our experiments show that the test sets generated for a particular circuit realization fail to detect in average only less than one and a half percent of the transition faults of the re-synthesized circuit. The possibilities of the reuse of functional delay test were studied as well.