SoC design methodology is totally dependent on the availability of reliable, easily interfaced and well supported IP cores. Complex cores such as microprocessors can be very expensive if licenced from commercial providers. Research projects, and even small companies, look for open source cores despite the problems associated with this source. The Rachael embedded processor discussed in this paper is a result of an open source initiative, supported both by a commercial design firm and a university. The processor is based on the proven SPARC architecture and was developed in Verilog with systematic methodology as used in industry. Rachael has a flexible memory architecture and is interfaced to the AMBA on chip bus. It is supported by a suite of development tools and is made available as an open source core. Rachel was extensively tested on Virtex4, an earlier version was used in a commercial chip, and a full version is to be fabricated.

We discuss architectural issues and trade-offs in the design of Rachael, present its architecture, and analyse performance factors. The Verilog pre-processor developed for the project is briefly introduced. The open source project is presented and analysed from both the university and industry perspectives. Rachael runs at speed on Xilinx?s ML401 board and it can be demonstrated executing various software applications.