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9th EUROMICRO Conference on Digital System Design (DSD'06)
A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems
Cavtat near Dubrovnik, Croatia
August 30-September 01
ISBN: 0-7695-2609-8
ASCII Text
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Roberto R. Osorio, Javier D. Bruguera, "A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems," Digital Systems Design, Euromicro Symposium on, pp. 269-274, 9th EUROMICRO Conference on Digital System Design (DSD'06), 2006.
 
 
BibTex
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@article{ 10.1109/DSD.2006.5,
author = {Roberto R. Osorio and Javier D. Bruguera},
title = {A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems},
journal ={Digital Systems Design, Euromicro Symposium on},
volume = {0},
year = {2006},
isbn = {0-7695-2609-8},
pages = {269-274},
doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2006.5},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Digital Systems Design, Euromicro Symposium on
TI - A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems
SN - 0-7695-2609-8
SP269
EP274
A1 - Roberto R. Osorio,
A1 - Javier D. Bruguera,
PY - 2006
KW - null
VL - 0
JA - Digital Systems Design, Euromicro Symposium on
ER -
 
Roberto R. Osorio, University of Santiago de Compostela, Spain
Javier D. Bruguera, University of Santiago de Compostela, Spain
In this paper a new technique is presented that combines memory compression in video encoders with fast and efficient motion estimation (ME). This technique is mainly oriented to embedded systems, which demand simple and power aware algorithms. Video encoding needs increasing amounts of memory for storing reference pictures. Memory compression allows reducing the footprint of the application, lowering the total implementation cost. In this paper, we combine memory compression and hierarchical ME so that the overhead associated to implement both techniques is shared. Thus, a net gain in processing speed is obtained, while reducing costs and power consumption.
Citation:
Roberto R. Osorio, Javier D. Bruguera, "A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems," dsd, pp.269-274, 9th EUROMICRO Conference on Digital System Design (DSD'06), 2006
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