This paper will describe the problems in the design and development of deep sub-100 nm system LSI?s and/or SoC?s from different aspects. One of the most difficult problems is the large power consumption, in both active and stand-by modes. Another problem is how to improve the efficiency in the development of large scale chips and related softwares. Lithography, that has been getting harder and harder, is also an issue. It directly impacts the chip fabrication yield. Several approaches to counteract these problems mentioned above will be discussed; various low power technologies from device, circuit to architecture view points, high-level language based design flow and platform based IP reuse, and DFM (Design for Manufacturing) related technologies.