loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
9th EUROMICRO Conference on Digital System Design (DSD'06)
Cascade Scheme for Concurrent Errors Detection
Cavtat near Dubrovnik, Croatia
August 30-September 01
ISBN: 0-7695-2609-8
Ilya Levin, Tel Aviv University, Israel
Vladimir Ostrovsky, Tel Aviv University, Israel
Osnat Keren, Bar Ilan University, Israel
Vladimir Sinelnikov, Bar Ilan University, Israel
The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades followed by parity checking their output logic. The algorithm for partitioning the scheme into cascades is provided.

An universal scheme of Finite State Machine (FSM) with the cascade errors detection is presented and investigated. The scheme does not require any redundant coding variables. Benchmark results are presented and show significantly low overhead requirement.

Citation:
Ilya Levin, Vladimir Ostrovsky, Osnat Keren, Vladimir Sinelnikov, "Cascade Scheme for Concurrent Errors Detection," dsd, pp.359-368, 9th EUROMICRO Conference on Digital System Design (DSD'06), 2006
Usage of this product signifies your acceptance of the Terms of Use.