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9th EUROMICRO Conference on Digital System Design (DSD'06)
Cascade Scheme for Concurrent Errors Detection
Cavtat near Dubrovnik, Croatia
August 30-September 01
ISBN: 0-7695-2609-8
ASCII Text
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Ilya Levin, Vladimir Ostrovsky, Osnat Keren, Vladimir Sinelnikov, "Cascade Scheme for Concurrent Errors Detection," Digital Systems Design, Euromicro Symposium on, pp. 359-368, 9th EUROMICRO Conference on Digital System Design (DSD'06), 2006.
 
 
BibTex
x
 
@article{ 10.1109/DSD.2006.31,
author = {Ilya Levin and Vladimir Ostrovsky and Osnat Keren and Vladimir Sinelnikov},
title = {Cascade Scheme for Concurrent Errors Detection},
journal ={Digital Systems Design, Euromicro Symposium on},
volume = {0},
year = {2006},
isbn = {0-7695-2609-8},
pages = {359-368},
doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2006.31},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Digital Systems Design, Euromicro Symposium on
TI - Cascade Scheme for Concurrent Errors Detection
SN - 0-7695-2609-8
SP359
EP368
A1 - Ilya Levin,
A1 - Vladimir Ostrovsky,
A1 - Osnat Keren,
A1 - Vladimir Sinelnikov,
PY - 2006
KW - null
VL - 0
JA - Digital Systems Design, Euromicro Symposium on
ER -
 
Ilya Levin, Tel Aviv University, Israel
Vladimir Ostrovsky, Tel Aviv University, Israel
Osnat Keren, Bar Ilan University, Israel
Vladimir Sinelnikov, Bar Ilan University, Israel
The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades followed by parity checking their output logic. The algorithm for partitioning the scheme into cascades is provided.

An universal scheme of Finite State Machine (FSM) with the cascade errors detection is presented and investigated. The scheme does not require any redundant coding variables. Benchmark results are presented and show significantly low overhead requirement.

Citation:
Ilya Levin, Vladimir Ostrovsky, Osnat Keren, Vladimir Sinelnikov, "Cascade Scheme for Concurrent Errors Detection," dsd, pp.359-368, 9th EUROMICRO Conference on Digital System Design (DSD'06), 2006
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