Todays? highly complex Systems-on-Chip require highspeed switching interconnects. Advances on signaling technology on the other hand allows the building of high-degree switching fabrics. Buffered crossbars are receiving increasing attention in these areas since they allow efficient highperformance distributed scheduling by decoupling inputs from outputs. However, the requirements in memory storage scale quadratically with the number of ports. An efficient architecture is presented to maximize system performance and memory utilization at the same time. The proposed solution is to integrate a shared memory buffer per row in addition to a minimum-sized dedicated buffer per crosspoint. An efficient novel architecture of an 8x8 crossbar switch is described, that is feasible and provides 100Gbps throughput implemented in a 0.18um CMOS technolo