9th EUROMICRO Conference on Digital System Design (DSD'06) A RISC Processor with Redundant LNS Instructions Cavtat near Dubrovnik, Croatia August 30-September 01 ISBN: 0-7695-2609-8
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2006.15
This paper presents Verilog code and FPGA synthesis results for a 32-bit RISC processor (RAWE) that uses the Dual Redundant Logarithmic Number System (DRLNS). A benchmark shows pure-software logarithmic arithmetic can be faster than floating point in some applications. An earlier processor (AWE) doubles that speed using hardware support for unsigned LNS values. Here, modest additional hardware allows the proposed RAWE to do signed multiply accumulate two to three times faster than AWE.
Citation:
Mark G. Arnold, "A RISC Processor with Redundant LNS Instructions," dsd, pp.475-482, 9th EUROMICRO Conference on Digital System Design (DSD'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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