A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA Blocks

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	Similar Articles Articles by Lucia Bissi Articles by Pisana Placidi Articles by Giuseppe Baruffa Articles by Andrea Scorzoni

9th EUROMICRO Conference on Digital System Design (DSD'06)

Cavtat near Dubrovnik, Croatia

August 30-September 01

ISBN: 0-7695-2609-8

	ASCII Text	x
	Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, Andrea Scorzoni, "A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA Blocks," Digital Systems Design, Euromicro Symposium on, pp. 146-154, 9th EUROMICRO Conference on Digital System Design (DSD'06), 2006.

	BibTex	x
	@article{ 10.1109/DSD.2006.12, author = {Lucia Bissi and Pisana Placidi and Giuseppe Baruffa and Andrea Scorzoni}, title = {A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA Blocks}, journal ={Digital Systems Design, Euromicro Symposium on}, volume = {0}, year = {2006}, isbn = {0-7695-2609-8}, pages = {146-154}, doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2006.12}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Digital Systems Design, Euromicro Symposium on TI - A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA Blocks SN - 0-7695-2609-8 SP146 EP154 A1 - Lucia Bissi, A1 - Pisana Placidi, A1 - Giuseppe Baruffa, A1 - Andrea Scorzoni, PY - 2006 KW - null VL - 0 JA - Digital Systems Design, Euromicro Symposium on ER -

Lucia Bissi, Universit? degli Studi di Perugia, Italy

Pisana Placidi, Universit? degli Studi di Perugia, Italy

Giuseppe Baruffa, Universit? degli Studi di Perugia, Italy

Andrea Scorzoni, Universit? degli Studi di Perugia, Italy

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2006.12

This paper presents a Viterbi Decoder (VD) architecture for a reprogrammable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has been conceived as a building block of a Software Defined Radio (SDR) mobile transceiver, reconfigurable on user request and capable to provide agility in choosing between different standards. UMTS and GPRS standards decoding is achieved by choosing different coding rates and constraint lengths, and the possibility to switch, at run time, between them guarantees a high degree of reconfigurability. The architecture has been tested and verified with a Xilinx XC2V2000 FPGA, to provide a generalized co-simulation/co-design testbed. The results show that this decoder can sustain an uncoded data rate of about 2 Mbps, with an area occupation of 45%, due to the efficient resource reuse.

Citation:

Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, Andrea Scorzoni, "A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA Blocks," dsd, pp.146-154, 9th EUROMICRO Conference on Digital System Design (DSD'06), 2006

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