9th EUROMICRO Conference on Digital System Design (DSD'06) A Monitoring-Aware Network-on-Chip Design Flow Cavtat near Dubrovnik, Croatia August 30-September 01 ISBN: 0-7695-2609-8
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2006.11
Networks-on-chip (NoC) are a scalable interconnect solution for systems on chip and are rapidly becoming reality. Monitoring is a key enabler for debugging or performance analysis and quality-of-service techniques. The NoC design problem and the NoC monitoring problem cannot be treated in isolation. We propose a monitoring-aware NoC design flow able to take into account the monitoring requirements in general. We illustrate our flow with a debug driven monitoring case study of transaction monitoring. By treating the NoC design and monitoring problems in synergy, the area cost of monitoring can be limited to 3-20% in general.
Citation:
Calin Ciordas, Andreas Hansson, Kees Goossens, Twan Basten, "A Monitoring-Aware Network-on-Chip Design Flow," dsd, pp.97-106, 9th EUROMICRO Conference on Digital System Design (DSD'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||