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8th Euromicro Conference on Digital System Design (DSD'05)
On LUT Cascade Realizations of FIR Filters
Porto, Portugal
August 30-September 03
ISBN: 0-7695-2433-8
ASCII Text
x 
 
Tsutomu Sasao, Yukihiro Iguchi, Takahiro Suzuki, "On LUT Cascade Realizations of FIR Filters," Digital Systems Design, Euromicro Symposium on, pp. 467-475, 8th Euromicro Conference on Digital System Design (DSD'05), 2005.
 
 
BibTex
x
 
@article{ 10.1109/DSD.2005.82,
author = {Tsutomu Sasao and Yukihiro Iguchi and Takahiro Suzuki},
title = {On LUT Cascade Realizations of FIR Filters},
journal ={Digital Systems Design, Euromicro Symposium on},
volume = {0},
year = {2005},
isbn = {0-7695-2433-8},
pages = {467-475},
doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2005.82},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Digital Systems Design, Euromicro Symposium on
TI - On LUT Cascade Realizations of FIR Filters
SN - 0-7695-2433-8
SP467
EP475
A1 - Tsutomu Sasao,
A1 - Yukihiro Iguchi,
A1 - Takahiro Suzuki,
PY - 2005
KW - null
VL - 0
JA - Digital Systems Design, Euromicro Symposium on
ER -
 
Tsutomu Sasao, Kyushu Institute of Technology
Yukihiro Iguchi, Meiji University
Takahiro Suzuki, Meiji University

This paper first defines the n-input q-output WS function, as a mathematical model of the combinational part of the distributed arithmetic of a finite impulse response (FIR) filter. Then, it shows a method to realize theWS function by an LUT cascade with k-input q-output cells. Furthermore, it 1) shows that LUT cascade realizations require much smaller memory than the single ROM realizations; 2) presents new design method for a WS function by arithmetic decomposition, and 3) shows design results of FIR filters using FPGAs with embedded memories.

Citation:
Tsutomu Sasao, Yukihiro Iguchi, Takahiro Suzuki, "On LUT Cascade Realizations of FIR Filters," dsd, pp.467-475, 8th Euromicro Conference on Digital System Design (DSD'05), 2005
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