Yield is normally ignored during the floorplanning stage. Recently, it has been shown that floorplanning can affect the yield with the increased sizes of chips. With the "medium-area clustering" model [1], yield can be evaluated during the floorplanning stage. Therefore, it?s straightforward to incorporate yield in modern floorplanners. However, conventional Simulate-Annealing(SA) based moves are only designed for the combination of the area and/or the wire length minimizations. In this paper, we proposed a heuristic scheme of "moves" directly targeting on the yield improvement. The experimental results show a great yield improvement with little penalty for the area and/or the total wire length.