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8th Euromicro Conference on Digital System Design (DSD'05)
State Assignment for PAL-based CPLDs
Porto, Portugal
August 30-September 03
ISBN: 0-7695-2433-8
Robert Czerwinski, Institute of Electronics, Silesian University of Technology
Dariusz Kania, Institute of Electronics, Silesian University of Technology

In the paper, the state assignment methods of the finite state machines for PAL-based structures are presented. A main feature of the PAL-cell is a limited number of product terms (k-AND-gates) that are connected to a single sum (OR-gate). Function,which is the sumof p-implicants, when p \ne k, does not take full advantage of the cell. When p \ge k, implementation is multi-cell (so multi-level). The main idea of solving this problem is to count the number of product terms during the process of state assignment. First algorithm leads to automata which take advantage of the number of PAL-cell terms. Second approach is dedicated to state assignment of fast automata. Methods based on Primary and Secondary Merging Conditions are presented. In one of the most basic states of the logic synthesis of sequential devices, the elements referring to restrictions of PAL-based CPLDs are taken into account.

Citation:
Robert Czerwinski, Dariusz Kania, "State Assignment for PAL-based CPLDs," dsd, pp.127-134, 8th Euromicro Conference on Digital System Design (DSD'05), 2005
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