Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming

D
DSD
2005
8th Euromicro Conference on Digital System Design (DSD'05)
Abstract - Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming

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8th Euromicro Conference on Digital System Design (DSD'05)

Porto, Portugal

August 30-September 03

ISBN: 0-7695-2433-8

	ASCII Text	x
	Tun Li, Yang Guo, GongJie Liu, SiKun Li, "Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming," Digital Systems Design, Euromicro Symposium on, pp. 17-25, 8th Euromicro Conference on Digital System Design (DSD'05), 2005.

	BibTex	x
	@article{ 10.1109/DSD.2005.43, author = {Tun Li and Yang Guo and GongJie Liu and SiKun Li}, title = {Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming}, journal ={Digital Systems Design, Euromicro Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2433-8}, pages = {17-25}, doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2005.43}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Digital Systems Design, Euromicro Symposium on TI - Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming SN - 0-7695-2433-8 SP17 EP25 A1 - Tun Li, A1 - Yang Guo, A1 - GongJie Liu, A1 - SiKun Li, PY - 2005 KW - null VL - 0 JA - Digital Systems Design, Euromicro Symposium on ER -

Tun Li, National University of Defense Technology, China

Yang Guo, National University of Defense Technology, China

GongJie Liu, National University of Defense Technology, China

SiKun Li, National University of Defense Technology, China

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2005.43

This paper presents a novel method for automatic functional vectors generation from RT-Level HDL descriptions based on path coverage and constraint solving. Compared with existing method, the advantage of this method includes: 1) it avoids generating redundant constraints, which will accelerate the test generation process. 2) it solves the problem of how to propagate the internal values to the primary inputs with decision models. 3) it can handle various HDL description styles, and various styles of designs. Experimental results conduct on several practical designs show that our method can efficiently improve the functional vectors generation process. The prototype system has been applied to verify RTL description of a real 32-bits microprocessor core and complex bugs remained hidden in the RTL descriptions are detected.

Citation:

Tun Li, Yang Guo, GongJie Liu, SiKun Li, "Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming," dsd, pp.17-25, 8th Euromicro Conference on Digital System Design (DSD'05), 2005

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