The same circuit may be described at algorithmic, behavioral or gate level. Test generation is usually performed for every level separately. We introduce a test generation approach based on test selection by means of simulation at algorithmic level of circuit description. The generated test could be applied to VHDL behavioral level as test bench. This test shows high fault coverage at equivalent gate level. The test selection procedure relies on the model of input stuck-at faults transmissions to output. The application of test frames allows sequential circuits to consider like combinational ones. The proposed method is implemented in the test generation program that is available on the Internet as freeware. The experiment shows efficiency of the proposed method.