The recent growth of cellular phone systems, voice over IP devices, and other multimedia applications has created a considerable need for efficient voice coding algorithms. These algorithms usually require intensive amount of signal processing capabilities and demand significant signal processing power. The current market trend of integrating multiple voice channels into a single die has further intensified the need for more powerful hardware platforms. Some new design ideas such as vocoderspecialized DSP architectures, combined RISC/DSP platforms, and adding hardware accelerators or coprocessors to the general-purpose processors have been proposed. In this paper, a new hardware accelerator design has been proposed which executes Macro Instructions (MIs). The proposed coprocessor can be added to each processor type that can support at least one coprocessor without modifying the compiler and redesigning the processor. It can handle computationally intensive loops in speech coding algorithms parallel with the main processor. The coprocessor along with software optimization reduces clock cycles required for G.723.1 by 80% and G.729 by 64% while MIPS R3000 RISC is used as the host.